Codasip Partners with Siemens to Supercharge Custom Processor Debugging

In an industry-defining collaboration, Codasip, a front-runner in RISC-V Custom Compute, and Siemens EDA, a giant in embedded analytics, have come together to enhance the debugging capabilities for custom processors. The partnership aims to integrate Siemens’ Tessent Enhanced Trace Encoder solution into Codasip’s bespoke RISC-V cores, offering unparalleled debugging and tracing functionalities to developers.

The Codasip RISC-V processors, well-known for their customizability, provide a toolkit for system designers to make optimal choices in software and hardware trade-offs. Codasip Studio’s suite of design tools serves to balance the key elements of Power, Performance, and Area (PPA), thereby accelerating the automation of Custom Compute. This focus on customization now extends to debugging and tracing solutions, further enhancing the utility of Codasip’s products for software developers.

The integration of trace functionality in System-on-Chips (SoCs) aims to slash the time and financial resources normally allocated for debugging software. The Tessent Enhanced Trace Encoder from Siemens is Codasip’s solution of choice for this endeavor, owing to a shared emphasis on efficiency and product quality throughout the design process. This collaboration promises significant productivity boosts even in the arena of highly complex and customized designs.

The Tessent Enhanced Trace Encoder doesn’t just conform to the RISC-V standard initiated by the Debug and Trace Working Group; it elevates it. The Siemens solution provides a highly efficient tool that conducts in-depth system analyses to find and address the root causes of bugs. Furthermore, its cycle-accurate design offers developers a meticulous look into every instruction that passes through the processor.

“Quality has always been a non-negotiable aspect of our processor IPs,” said Mike Eftimakis, VP Strategy and Ecosystem at Codasip. “The Tessent Enhanced Trace Encoder aligns perfectly with our mission, as it offers far more than the standard RISC-V solutions and is optimized for the complex systems our clients are developing.”

Ankur Gupta, VP and GM of Siemens EDA’s Tessent division, noted, “Our platform allows for real-time debugging and post-deployment analytics, aiding SoC providers in delivering high-quality, innovative products quickly. We couldn’t have found a better partner than Codasip for this endeavor.”

To streamline the user experience and eliminate contractual hurdles, Codasip plans to offer the Tessent Enhanced Trace Encoder solution directly to its clientele.

This joint venture between Codasip and Siemens EDA marks a pivotal step in custom processor development, emphasizing quality, efficiency, and customer productivity as the cornerstones of a new era in computing.

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